<html><body><samp><pre>
<!@TC:1289509804>
#Build: Synplify Pro C-2009.03A-2, Build 084R, May  3 2009
#install: C:\Actel\Libero_v8.6\Synplify\synplify_200903A2
#OS: Windows XP 5.1
#Hostname: TANDAICA0612

#Implementation: rev_1

#Fri Nov 12 04:10:01 2010

<a name=compilerReport1>$ Start of Compile</a>
#Fri Nov 12 04:10:01 2010

Synopsys VHDL Compiler, version comp400rc, Build 007R, built May  5 2009
Copyright (C) 1994-2009, Synopsys Inc.  All Rights Reserved

@N:<a href="@N:CD720:@XP_HELP">CD720</a> : <a href="C:\Actel\Libero_v8.6\Synplify\synplify_200903A2\lib\vhd\std.vhd:123:18:123:22:@N:CD720:@XP_MSG">std.vhd(123)</a><!@TM:1289509804> | Setting time resolution to ns
@N: : <a href="C:\Documents and Settings\tandaica0612\Desktop\UART\UARTRX.VHD:14:7:14:13:@N::@XP_MSG">UARTRX.VHD(14)</a><!@TM:1289509804> | Top entity is set to UartRx.
VHDL syntax check successful!

Compiler output is up to date.  No re-compile necessary

@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="C:\Documents and Settings\tandaica0612\Desktop\UART\UARTRX.VHD:14:7:14:13:@N:CD630:@XP_MSG">UARTRX.VHD(14)</a><!@TM:1289509804> | Synthesizing work.uartrx.uartrx_beh 
Post processing for work.uartrx.uartrx_beh
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Fri Nov 12 04:10:01 2010

###########################################################]
Synopsys Proasic Technology Mapper, Version map400act, Build 083R, Built May 22 2009 08:06:30
Copyright (C) 1994-2009, Synopsys Inc.  All Rights Reserved
Product Version C-2009.03A-2
@N:<a href="@N:MF249:@XP_HELP">MF249</a> : <!@TM:1289509804> | Running in 32-bit mode. 
@N:<a href="@N:MF258:@XP_HELP">MF258</a> : <!@TM:1289509804> | Gated clock conversion disabled  


Available hyper_sources - for debug and ip models
	None Found

@N:<a href="@N:MT206:@XP_HELP">MT206</a> : <!@TM:1289509804> | Autoconstrain Mode is ON 
Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 83MB peak: 83MB)

@N: : <a href="c:\documents and settings\tandaica0612\desktop\uart\uartrx.vhd:28:9:28:18:@N::@XP_MSG">uartrx.vhd(28)</a><!@TM:1289509804> | Found counter in view:work.UartRx(uartrx_beh) inst Count16_r[3:0]
Finished factoring (Time elapsed 0h:00m:00s; Memory used current: 83MB peak: 84MB)

Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:00s; Memory used current: 83MB peak: 84MB)

Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:00s; Memory used current: 83MB peak: 84MB)

Starting Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 83MB peak: 84MB)

Finished Early Timing Optimization (Time elapsed 0h:00m:01s; Memory used current: 83MB peak: 84MB)

Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:01s; Memory used current: 83MB peak: 84MB)

Finished preparing to map (Time elapsed 0h:00m:01s; Memory used current: 83MB peak: 84MB)


High Fanout Net Report
**********************

Driver Instance / Pin Name     Fanout, notes
--------------------------------------------
RxMT_r / Q                     14           
============================================

Promoting Net Clk16xT_c on GL33  Clk16xT_pad
Replicating Sequential Instance RxMT_r, fanout 14 segments 2
Finished technology mapping (Time elapsed 0h:00m:01s; Memory used current: 83MB peak: 84MB)

Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:01s; Memory used current: 83MB peak: 84MB)


Added 0 Buffers
Added 1 Cells via replication
	Added 1 Sequential Cells via replication
	Added 0 Combinational Cells via replication
Finished restoring hierarchy (Time elapsed 0h:00m:01s; Memory used current: 83MB peak: 84MB)

Writing Analyst data base D:\Learn VHDL\rev_1\UARTRX.srm
@N:<a href="@N:BN225:@XP_HELP">BN225</a> : <!@TM:1289509804> | Writing default property annotation file D:\Learn VHDL\rev_1\UARTRX.map. 
Finished Writing Netlist Databases (Time elapsed 0h:00m:01s; Memory used current: 83MB peak: 84MB)

Writing EDIF Netlist and constraint files
C-2009.03A-2
Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:00m:01s; Memory used current: 83MB peak: 84MB)

Found clock UartRx|Clk16xT with period 9.58ns 


<a name=timingReport2>##### START OF TIMING REPORT #####[</a>
# Timing Report written on Fri Nov 12 04:10:04 2010
#


Top view:               UartRx
Requested Frequency:    104.4 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N:<a href="@N:MT320:@XP_HELP">MT320</a> : <!@TM:1289509804> | This timing report estimates place and route data. Please look at the place and route timing report for final timing.. 

@N:<a href="@N:MT322:@XP_HELP">MT322</a> : <!@TM:1289509804> | Clock constraints cover only FF-to-FF paths associated with the clock.. 



<a name=performanceSummary3>Performance Summary </a>
*******************


Worst slack in design: -1.690

                   Requested     Estimated     Requested     Estimated                Clock        Clock                
Starting Clock     Frequency     Frequency     Period        Period        Slack      Type         Group                
------------------------------------------------------------------------------------------------------------------------
UartRx|Clk16xT     104.4 MHz     88.7 MHz      9.579         11.270        -1.690     inferred     Autoconstr_clkgroup_0
========================================================================================================================





<a name=clockRelationships4>Clock Relationships</a>
*******************

Clocks                          |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
-----------------------------------------------------------------------------------------------------------------------
Starting        Ending          |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
-----------------------------------------------------------------------------------------------------------------------
UartRx|Clk16xT  UartRx|Clk16xT  |  9.579       -1.691  |  No paths    -      |  No paths    -      |  No paths    -    
=======================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



<a name=interfaceInfo5>Interface Information </a>
*********************

		No IO constraint found 



====================================
<a name=clockReport6>Detailed Report for Clock: UartRx|Clk16xT</a>
====================================



<a name=startingSlack7>Starting Points with Worst Slack</a>
********************************

                 Starting                                             Arrival           
Instance         Reference          Type     Pin     Net              Time        Slack 
                 Clock                                                                  
----------------------------------------------------------------------------------------
Count16_r[0]     UartRx|Clk16xT     DFF      Q       Count16_r[0]     0.160       -1.690
Count16_r[1]     UartRx|Clk16xT     DFF      Q       Count16_r[1]     0.200       -1.351
RxMT_r_0_0       UartRx|Clk16xT     DFF      Q       RxMT_r_0         0.200       -0.685
Count16_r[2]     UartRx|Clk16xT     DFF      Q       Count16_r[2]     0.200       0.374 
Count16_r[3]     UartRx|Clk16xT     DFF      Q       Count16_r[3]     0.200       1.175 
RxIn_r           UartRx|Clk16xT     DFF      Q       RxIn_r           0.200       1.249 
RxMT_r           UartRx|Clk16xT     DFF      Q       RxMT_r           0.160       3.919 
RxReg_r[9]       UartRx|Clk16xT     DFF      Q       RxReg_r[9]       0.200       5.267 
RxReg_r[1]       UartRx|Clk16xT     DFF      Q       RxReg_r_c[1]     0.160       5.389 
RxReg_r[2]       UartRx|Clk16xT     DFF      Q       RxReg_r_c[2]     0.160       5.389 
========================================================================================


<a name=endingSlack8>Ending Points with Worst Slack</a>
******************************

               Starting                                      Required           
Instance       Reference          Type     Pin     Net       Time         Slack 
               Clock                                                            
--------------------------------------------------------------------------------
RxReg_r[0]     UartRx|Clk16xT     DFF      D       N_102     9.331        -1.690
RxReg_r[1]     UartRx|Clk16xT     DFF      D       N_103     9.331        -1.690
RxReg_r[2]     UartRx|Clk16xT     DFF      D       N_104     9.331        -1.690
RxReg_r[3]     UartRx|Clk16xT     DFF      D       N_105     9.331        -1.690
RxReg_r[4]     UartRx|Clk16xT     DFF      D       N_106     9.331        -1.690
RxReg_r[5]     UartRx|Clk16xT     DFF      D       N_107     9.331        -1.690
RxReg_r[6]     UartRx|Clk16xT     DFF      D       N_108     9.331        -1.690
RxReg_r[7]     UartRx|Clk16xT     DFF      D       N_109     9.331        -1.690
RxReg_r[8]     UartRx|Clk16xT     DFF      D       N_110     9.331        -1.690
RxReg_r[9]     UartRx|Clk16xT     DFF      D       N_111     9.331        -1.690
================================================================================



<a name=worstPaths9>Worst Path Information</a>
<a href="D:\Learn VHDL\rev_1\UARTRX.srr:fp:9851:11471:@XP_NAMES_GATE">View Worst Path in Analyst</a>
***********************


Path information for path number 1: 
    Requested Period:                        9.579
    - Setup time:                            0.248
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         9.331

    - Propagation time:                      11.022
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -1.691

    Number of logic level(s):                5
    Starting point:                          Count16_r[0] / Q
    Ending point:                            RxReg_r[0] / D
    The start point is clocked by            UartRx|Clk16xT [rising] on pin CLK
    The end   point is clocked by            UartRx|Clk16xT [rising] on pin CLK

Instance / Net                         Pin      Pin               Arrival     No. of    
Name                       Type        Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------
Count16_r[0]               DFF         Q        Out     0.160     0.160       -         
Count16_r[0]               Net         -        -       1.900     -           4         
Count16_r_n1_0_i_o3        AND2        A        In      -         2.060       -         
Count16_r_n1_0_i_o3        AND2        Y        Out     0.108     2.168       -         
N_86                       Net         -        -       1.480     -           3         
Count16_r_n2_0_i_o3        AND2        B        In      -         3.648       -         
Count16_r_n2_0_i_o3        AND2        Y        Out     0.180     3.828       -         
N_87                       Net         -        -       1.480     -           3         
Rx_Lbl\.un8_count16_r_0    AO21TTF     A        In      -         5.308       -         
Rx_Lbl\.un8_count16_r_0    AO21TTF     Y        Out     0.168     5.476       -         
Rx_Lbl\.un8_count16_r      Net         -        -       3.990     -           10        
RxReg_r_0[0]               MUX2H       S        In      -         9.466       -         
RxReg_r_0[0]               MUX2H       Y        Out     0.148     9.614       -         
N_27                       Net         -        -       0.630     -           1         
RxReg_r_1_i_a2[0]          OR2FT       B        In      -         10.244      -         
RxReg_r_1_i_a2[0]          OR2FT       Y        Out     0.148     10.392      -         
N_102                      Net         -        -       0.630     -           1         
RxReg_r[0]                 DFF         D        In      -         11.022      -         
========================================================================================
Total path delay (propagation time + ICD at startpoint + setup - ICD at endpoint) of 11.270 is 1.160(10.3%) logic and 10.110(89.7%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
*Arrival time includes intrinsic clock delay at start point and clock delay at startpoint


Path information for path number 2: 
    Requested Period:                        9.579
    - Setup time:                            0.248
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         9.331

    - Propagation time:                      11.022
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -1.691

    Number of logic level(s):                5
    Starting point:                          Count16_r[0] / Q
    Ending point:                            RxReg_r[1] / D
    The start point is clocked by            UartRx|Clk16xT [rising] on pin CLK
    The end   point is clocked by            UartRx|Clk16xT [rising] on pin CLK

Instance / Net                         Pin      Pin               Arrival     No. of    
Name                       Type        Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------
Count16_r[0]               DFF         Q        Out     0.160     0.160       -         
Count16_r[0]               Net         -        -       1.900     -           4         
Count16_r_n1_0_i_o3        AND2        A        In      -         2.060       -         
Count16_r_n1_0_i_o3        AND2        Y        Out     0.108     2.168       -         
N_86                       Net         -        -       1.480     -           3         
Count16_r_n2_0_i_o3        AND2        B        In      -         3.648       -         
Count16_r_n2_0_i_o3        AND2        Y        Out     0.180     3.828       -         
N_87                       Net         -        -       1.480     -           3         
Rx_Lbl\.un8_count16_r_0    AO21TTF     A        In      -         5.308       -         
Rx_Lbl\.un8_count16_r_0    AO21TTF     Y        Out     0.168     5.476       -         
Rx_Lbl\.un8_count16_r      Net         -        -       3.990     -           10        
RxReg_r_0[1]               MUX2H       S        In      -         9.466       -         
RxReg_r_0[1]               MUX2H       Y        Out     0.148     9.614       -         
N_28                       Net         -        -       0.630     -           1         
RxReg_r_1_i_a2[1]          OR2FT       B        In      -         10.244      -         
RxReg_r_1_i_a2[1]          OR2FT       Y        Out     0.148     10.392      -         
N_103                      Net         -        -       0.630     -           1         
RxReg_r[1]                 DFF         D        In      -         11.022      -         
========================================================================================
Total path delay (propagation time + ICD at startpoint + setup - ICD at endpoint) of 11.270 is 1.160(10.3%) logic and 10.110(89.7%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
*Arrival time includes intrinsic clock delay at start point and clock delay at startpoint


Path information for path number 3: 
    Requested Period:                        9.579
    - Setup time:                            0.248
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         9.331

    - Propagation time:                      11.022
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -1.691

    Number of logic level(s):                5
    Starting point:                          Count16_r[0] / Q
    Ending point:                            RxReg_r[2] / D
    The start point is clocked by            UartRx|Clk16xT [rising] on pin CLK
    The end   point is clocked by            UartRx|Clk16xT [rising] on pin CLK

Instance / Net                         Pin      Pin               Arrival     No. of    
Name                       Type        Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------
Count16_r[0]               DFF         Q        Out     0.160     0.160       -         
Count16_r[0]               Net         -        -       1.900     -           4         
Count16_r_n1_0_i_o3        AND2        A        In      -         2.060       -         
Count16_r_n1_0_i_o3        AND2        Y        Out     0.108     2.168       -         
N_86                       Net         -        -       1.480     -           3         
Count16_r_n2_0_i_o3        AND2        B        In      -         3.648       -         
Count16_r_n2_0_i_o3        AND2        Y        Out     0.180     3.828       -         
N_87                       Net         -        -       1.480     -           3         
Rx_Lbl\.un8_count16_r_0    AO21TTF     A        In      -         5.308       -         
Rx_Lbl\.un8_count16_r_0    AO21TTF     Y        Out     0.168     5.476       -         
Rx_Lbl\.un8_count16_r      Net         -        -       3.990     -           10        
RxReg_r_0[2]               MUX2H       S        In      -         9.466       -         
RxReg_r_0[2]               MUX2H       Y        Out     0.148     9.614       -         
N_29                       Net         -        -       0.630     -           1         
RxReg_r_1_i_a2[2]          OR2FT       B        In      -         10.244      -         
RxReg_r_1_i_a2[2]          OR2FT       Y        Out     0.148     10.392      -         
N_104                      Net         -        -       0.630     -           1         
RxReg_r[2]                 DFF         D        In      -         11.022      -         
========================================================================================
Total path delay (propagation time + ICD at startpoint + setup - ICD at endpoint) of 11.270 is 1.160(10.3%) logic and 10.110(89.7%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
*Arrival time includes intrinsic clock delay at start point and clock delay at startpoint


Path information for path number 4: 
    Requested Period:                        9.579
    - Setup time:                            0.248
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         9.331

    - Propagation time:                      11.022
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -1.691

    Number of logic level(s):                5
    Starting point:                          Count16_r[0] / Q
    Ending point:                            RxReg_r[3] / D
    The start point is clocked by            UartRx|Clk16xT [rising] on pin CLK
    The end   point is clocked by            UartRx|Clk16xT [rising] on pin CLK

Instance / Net                         Pin      Pin               Arrival     No. of    
Name                       Type        Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------
Count16_r[0]               DFF         Q        Out     0.160     0.160       -         
Count16_r[0]               Net         -        -       1.900     -           4         
Count16_r_n1_0_i_o3        AND2        A        In      -         2.060       -         
Count16_r_n1_0_i_o3        AND2        Y        Out     0.108     2.168       -         
N_86                       Net         -        -       1.480     -           3         
Count16_r_n2_0_i_o3        AND2        B        In      -         3.648       -         
Count16_r_n2_0_i_o3        AND2        Y        Out     0.180     3.828       -         
N_87                       Net         -        -       1.480     -           3         
Rx_Lbl\.un8_count16_r_0    AO21TTF     A        In      -         5.308       -         
Rx_Lbl\.un8_count16_r_0    AO21TTF     Y        Out     0.168     5.476       -         
Rx_Lbl\.un8_count16_r      Net         -        -       3.990     -           10        
RxReg_r_0[3]               MUX2H       S        In      -         9.466       -         
RxReg_r_0[3]               MUX2H       Y        Out     0.148     9.614       -         
N_30                       Net         -        -       0.630     -           1         
RxReg_r_1_i_a2[3]          OR2FT       B        In      -         10.244      -         
RxReg_r_1_i_a2[3]          OR2FT       Y        Out     0.148     10.392      -         
N_105                      Net         -        -       0.630     -           1         
RxReg_r[3]                 DFF         D        In      -         11.022      -         
========================================================================================
Total path delay (propagation time + ICD at startpoint + setup - ICD at endpoint) of 11.270 is 1.160(10.3%) logic and 10.110(89.7%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
*Arrival time includes intrinsic clock delay at start point and clock delay at startpoint


Path information for path number 5: 
    Requested Period:                        9.579
    - Setup time:                            0.248
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         9.331

    - Propagation time:                      11.022
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -1.691

    Number of logic level(s):                5
    Starting point:                          Count16_r[0] / Q
    Ending point:                            RxReg_r[4] / D
    The start point is clocked by            UartRx|Clk16xT [rising] on pin CLK
    The end   point is clocked by            UartRx|Clk16xT [rising] on pin CLK

Instance / Net                         Pin      Pin               Arrival     No. of    
Name                       Type        Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------
Count16_r[0]               DFF         Q        Out     0.160     0.160       -         
Count16_r[0]               Net         -        -       1.900     -           4         
Count16_r_n1_0_i_o3        AND2        A        In      -         2.060       -         
Count16_r_n1_0_i_o3        AND2        Y        Out     0.108     2.168       -         
N_86                       Net         -        -       1.480     -           3         
Count16_r_n2_0_i_o3        AND2        B        In      -         3.648       -         
Count16_r_n2_0_i_o3        AND2        Y        Out     0.180     3.828       -         
N_87                       Net         -        -       1.480     -           3         
Rx_Lbl\.un8_count16_r_0    AO21TTF     A        In      -         5.308       -         
Rx_Lbl\.un8_count16_r_0    AO21TTF     Y        Out     0.168     5.476       -         
Rx_Lbl\.un8_count16_r      Net         -        -       3.990     -           10        
RxReg_r_0[4]               MUX2H       S        In      -         9.466       -         
RxReg_r_0[4]               MUX2H       Y        Out     0.148     9.614       -         
N_31                       Net         -        -       0.630     -           1         
RxReg_r_1_i_a2[4]          OR2FT       B        In      -         10.244      -         
RxReg_r_1_i_a2[4]          OR2FT       Y        Out     0.148     10.392      -         
N_106                      Net         -        -       0.630     -           1         
RxReg_r[4]                 DFF         D        In      -         11.022      -         
========================================================================================
Total path delay (propagation time + ICD at startpoint + setup - ICD at endpoint) of 11.270 is 1.160(10.3%) logic and 10.110(89.7%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
*Arrival time includes intrinsic clock delay at start point and clock delay at startpoint



##### END OF TIMING REPORT #####]

--------------------------------------------------------------------------------
Target Part: A500K050
Report for cell UartRx.uartrx_beh
  Core Cell usage:
              cell count     area count*area
              AND2     2      1.0        2.0
           AND3FFT     1      1.0        1.0
           AO21TTF     1      1.0        1.0
               GND     1      0.0        0.0
               INV     1      1.0        1.0
             MUX2H    11      1.0       11.0
             NAND2     2      1.0        2.0
              NOR2     5      1.0        5.0
              NOR3     3      1.0        3.0
               OR2    11      1.0       11.0
             OR2FT    11      1.0       11.0
               PWR     1      0.0        0.0
            XOR2FT     1      1.0        1.0


               DFF    18      1.0       18.0
                   -----          ----------
             TOTAL    69                67.0


  IO Cell usage:
              cell count
              GL33     1
              IB33     2
            OB33PH    10
                   -----
             TOTAL    13


Core Cells         : 67 of 5376 (1%)
IO Cells           : 13 of 204 (6%)

  RAM/ROM Usage Summary
Block Rams : 0 of 6 (0%)

Mapper successful!
Process took 0h:00m:02s realtime, 0h:00m:01s cputime
# Fri Nov 12 04:10:04 2010

###########################################################]
